During typical semiconductor manufacturing processes, a plurality of integrated circuits are formed as individual dice on a semiconductor wafer. Each semiconductor wafer generally has hundreds to thousands of individual dice formed thereon. Each dice, particularly those providing system-on-chip (SoC) or application specific integrated circuits (ASIC), may include a plurality of blocks, such as to provide different functionality. For example, each dice may include one or more blocks of circuitry for providing digital processing as well as one or more blocks of circuitry for providing analog or radio frequency (RF) processing.
Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional and which dice are not functional (this procedure is sometimes referred to as “wafer sort”). The purpose of the wafer-level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less time and expense that is wasted on further processing of defective dice. That is, if it is determined that a detected defect cannot be repaired, the time and expense of completing a chip assembly will not be expended.
In most testing procedures, each die or device under test (DUT) is probed using very costly probe equipment while the dice are still on the wafer. In traditional testing procedures, probe equipment is used to contact each bonding pad (or “access pad”) on an individual die with a separate probe needle or pin. More specifically, in traditional testing procedures, each die or discrete block of circuitry thereof (circuitry under test (CUT)) is probed in order to determine whether it passes a very basic test (e.g., a test for electrical opens or electrical shorts). In most cases, a full functional test may also be performed using the probe equipment. A probe (which may also be referred to as a “stylus”) may be brought into contact with one or more bonding pads of a die in order to communicate signals (e.g., a test pattern) to the die and to receive the signals output by the die responsive to the input signals. The probe may be communicatively coupled to automated test equipment (ATE) that is operable to generate the signals to be input to a die and to evaluate the signals output by the die in order to determine whether the die is functioning properly.
Traditional testing procedures generally involve contacting access pad(s) of each individual die with a probe in series. That is, the dice of a wafer are generally tested one at a time in series using a probe to contact the pad(s) of each die. However, traditional testing procedures are problematic because of their serial nature. For example, using a probe to test one die after another die results in an undesirably long time being required for testing all of the dice of a wafer, which effectively increases the overall cost of testing the dice. Probes, and their attendant resources, used for testing the dice are generally very expensive, and it is therefore undesirable to have a probe tied up for a long time testing the dice of a single wafer.
Further, the life of a probe is generally measured by the number of times it touches down on dice (e.g., a probe may have a typical life of one million touch downs). Traditional testing procedures that require a probe to touch down on one (or a few) dice at a time effectively increases the wear of a probe. For instance, a probe having a life of one million touch downs that is utilized in a traditional testing procedure in which one die at a time is tested will be capable of testing one million dice. Considering the cost associated with such probes, it is generally desirable to effectively prolong the life of a probe by testing as many dice as possible during the probe's life. Moreover, single (or a few) dice testing requires longer testing times as the probe must be moved to a die and conduct the appropriate testing, move to another die and conduct the appropriate testing, etcetera.
From the above, it can appreciated that it is generally desirable to test a number of dice in parallel. Accordingly, more recently, testing techniques have been proposed that enable parallel testing of multiple dice of a wafer with a single probe. Examples of such parallel testing schemes that have been proposed include those described in U.S. Pat. No. 6,426,904 entitled “Structures for Wafer Level Test and Burn-In” issued Jul. 30, 2002 to Barth, et al., U.S. Pat. No. 6,275,051 entitled “Segmented Architecture for Wafer Test and Burn-In” issued Aug. 14, 2001 to Bachelder, et al., U.S. Pat. No. 6,134,685 entitled “Package Parallel Test Method and Apparatus” issued Oct. 17, 2000 to Spano, and U.S. Pat. No. 5,896,040 entitled “Configurable Probe Pads to Facilitate Parallel Testing of Integrated Circuit Devices” issued Apr. 20, 1999 to Brannigan, et al., the disclosures of which are hereby incorporated herein by reference.
In providing a parallel testing implementation, a probe may comprise a sufficient number of pins to enable access pads of multiple dice to be contacted simultaneously for testing of such multiple dice and the ATE associated therewith may comprise a number of resources, such as test signal generators and output signal analyzers, to enable testing of multiple dice simultaneously. In implementing such parallel testing, a test sequence is typically established for testing the discrete blocks or CUTs of the dice or DUTs, and this same static test sequence is employed with respect to each die of the wafer.
Discrete blocks or CUTs of the dice or DUTs may be analyzed to determine which blocks may be tested in parallel (e.g., digital blocks) and which blocks may not be suitable for parallel testing (e.g., analog blocks, such as due to radio frequency (RF) mutual interference, due to lack of ATE resources, etcetera). Using such information, parallel testing according to the prior art is implemented to employ the aforementioned test sequence with respect to each die of a set of dice being tested in parallel such that only those blocks compatible with parallel testing are tested simultaneously in parallel and those blocks incompatible with simultaneous parallel testing are tested serially. Accordingly, such prior art solutions, relying upon a same static test sequence for each die of a set of dice being tested, do not achieve maximum parallelism but instead provide an often non-optimized hybrid parallel/serial test technique.
Additionally, while certain probe implementations may provide a sufficient number of pins to enable a plurality of dice to be tested simultaneously, such testing is limited by the resources available at the ATE. For instance, a probe that comprises sufficient pins for contacting two dice simultaneously may be prevented from actually testing the two dice, or blocks thereof, due to a lack of redundancy of a particular resource necessary for testing at the ATE. For example, RF circuitry test apparatus is often very expensive whereas digital test apparatus is relatively inexpensive, resulting in multiple digital test resources being available while only a few or even a single RF test resource is available at the ATE. Accordingly, testing may be limited serial testing due to limitations associated with the available resources, thereby requiring longer test times and preventing certain parallel testing scenarios.
Semiconductor manufacturers spend a significant amount of money packaging defective dice which pass the testing performed during probing, but which do not pass subsequent reliability testing after packaging. The cost saving goal of detecting and screening out defective dice as early as possible in the manufacturing process is especially important in the context of multi-chip modules (MCMs), e.g., the aforementioned SoCs. Multi-chip modules (MCMs) are electronic modules that include a plurality of integrated circuit dice which are packaged together as one unit. Multi-chip modules are becoming more widely used.
For multi-chip modules, it is quite costly to replace one or more failed dice once the dice have been bonded onto a substrate. Therefore, it is desirable to determine whether a die is fully functional and is reliable before the die is packaged as part of a multi-chip module. In addition, many manufacturers of multi-chip modules are requiring that semiconductor manufacturers sell them fully tested “known good dice” that have passed reliability tests and that are not packaged in an integrated circuit package.